A collection of manufacturers have announced the formation of a working group committed to creating an open standard for next-generation memory interface technology targeting mobile phones. This memory standard for dynamic random access memory (DRAM), named Serial Port Memory Technology (SPMT) should significantly reduced pin count, lower power demand and multiple ports by using a serial interface instead of the parallel interface commonly used in today's memory devices.
The group says that this technology will be ideal for mobile handset manufacturers and consumers because it will dramatically extend battery life while allowing high- performance media-rich applications that will be the norm on next-generation mobile phones.
The group has been formed by ARM, Hynix Semiconductor, LG Electronics, Samsung Electronics, Silicon Image, Sony Ericsson and ST Microelectronics.
The SPMT Working Group's goal is to define a technology that reduces pin count by a minimum of 40 percent, provides a bandwidth range from 3.2GB/s to 12.6GB/s and higher, reduces input/output power by 50 percent or more to extend battery life, and provides the ability to use either a single port or multiple ports into a single SPMT-enabled memory chip.
While initially targeted at the mobile handset market, the technology will also be in demand by other markets such as portable media players, digital still cameras and handheld gaming devices.
"The need for faster, denser DRAM chips for handsets will continue to grow, particularly as the requirement for media-rich functionality escalates," said Nam Hyung Kim, memory analyst, iSuppli. "It makes sense to develop an interface standard for DRAM integrating serial technology that offers a way to achieve higher bandwidth, pin count reduction and scalability not achievable with current interface technologies."
Posted to the site on 29th April 2008