New 3G Subsystem Launched

Analog Devices has introduced a wideband receiver subsystem for cellular base stations that addresses the demanding performance requirements of 3G standards, such as CDMA2000, UMTS, and TD-SCDMA. Analog Devices' new mixed-signal device--the AD6654--combines the industry's highest performance 14-bit analog-to-digital converter (ADC) with a four- or six-channel digital down-converter (DDC). This highly integrated solution enables efficient processing of multi-carrier standards by removing the traditional interconnect issues associated with high-speed data transfer from the ADC to the DDC. In addition, the integrated device reduces the bill of material (BOM) components count, which can translate into a 20 percent saving in cost over individual components.

The analog core of the AD6654 contains ADI's industry-leading high-speed 14-bit ADC (the AD6645), which operates at more than 92 MSPS, while the digital function is performed by a DDC.

The ADC stage features a high-performance track-and-hold input amplifier, precision integrated voltage reference and 14-bit sampling resolution. Input signals up to 200 MHz may be accurately digitized at 92.16 MSPS rate using under-sampling techniques. Its signal-to-noise (SNR) ratio is 74.5 dB (to Nyquist), and its multi-tone spurious-free dynamic range (SFDR) is 100 dB (to 2x Nyquist). ADC data outputs are directly tied to the receiver input where down-conversion, decimation and digital filtering are performed.

"The year 2004 will be a critical year for the growth of 3G technology markets. Mobile network operators are seeking cost-effective solutions from their equipment makers, while equipment makers are challenged with building systems that can operate over the broadest range of 3G services," said David Robertson, product line director for high-speed converters in communications, Analog Devices, Inc. "To meet this challenge, Analog Devices has leveraged our integration expertise, combining two of our most powerful devices into one complete, high-performance solution that reduces both component count and system complexity.

The AD6654's digital down-converter can process four or six CDMA2000, UMTS, or TD/SCDMA channels simultaneously. Each channel is dynamically reconfigurable, operates independently, and includes cascaded signal-processing elements: a frequency translator, programmable decimating filter, and automatic gain control (AGC) circuitry that optimizes the dynamic range of the system. The receiver input block allows routing of the ADC data to any or all of the six receive processing channels.

The AD6654 features a fractional clock multiplier that uses the ADC clock to produce a digital down converter master clock up to 200 MHz. This internal phase-locked loop (PLL) allows optimum digital clock rates, regardless of the converter sampling rate, enabling the best possible digital signal decimation and filtering. Two 16-bit parallel output ports accommodate high data rate 3G applications. An on-chip interpolating half band can also be used to further increase the output rate while still allowing for very efficient filters. In addition, each parallel output port has a digital AGC for output data scaling.

The AD6654 is sampling now, and production quantities will be available in the first quarter of 2004."

Posted to the site on 6th November 2003